1. Field of the Invention
The present invention relates to a scrambling/descrambling circuit for data transmission using a clock recovery or self-clocking technique.
2. Description of the Prior Art
FIG. 8 is a block diagram of a typical conventional data transmission system. In FIG. 8, a transmitting side processing circuit 31 receives data to be transmitted, such as audio data and video data. The processing circuit 31 encodes and multiplexes the received data for output. A scrambling circuit 32 scrambles the data coming from the transmitting side processing circuit 31 and outputs the scrambled data to a modulator 33. The modulator 33 modulates the received data in accordance with a predetermined format and places the modulated data onto transmission lines of satellite, optical fiber and microwave circuits and the like.
A demodulator 34 demodulates the received signal and sends the demodulated data to a descrambling circuit 35. The descrambling circuit 35 descrambles the data it receives and outputs the descrambled data to a receiving side processing circuit 36. The receiving side processing circuit 36 decodes and branches the descrambled data it receives into the original audio data, video data and others.
A bit clock reproduction circuit 37 reproduces a bit clock signal from the data it receives from the demodulator 34. The bit clock signal is sent to a frame synchronization protection circuit 38, to the descrambling circuit 35 and to the receiving side processing circuit 36. The frame synchronization protection circuit 38 detects a frame signal from the data it receives from the demodulator 34. The detected frame signal is output to the descrambling circuit 35 and the receiving side processing circuit 36. The descrambling circuit 35 and the receiving side processing circuit 36 perform various kinds of processing by use of the reproduced bit clock signal from the bit clock reproduction circuit 37 and of the detected frame signal from the frame synchronization protection circuit 38.
As described, bit clock reproduction on the receiving side is made easier by having the scrambling circuit 32 scramble output data.
The scrambling circuit 32 (descrambling circuit 35) is illustratively constructed as shown in FIG. 9. The scrambling (descrambling) circuit of FIG. 9 comprises delay circuits 32a through 32e, for successively delaying input data by one clock pulse each before output, and exclusive-OR gates 32f and 32g.
The output of the delay circuit 32e is supplied to the delay circuit 32d, the output of the latter being forwarded to the delay circuit 32c. Likewise, the output of the delay circuit 32c is sent to the delay circuit 32b whose output is in turn fed to the delay circuit 32a. The output of the delay circuit 32c and that of the delay circuit 32a are input to the exclusive-OR gate 32f. The output of the exclusive-OR gate 32f is input to the delay circuit 32e. The output of the delay circuit 32a is taken as a scramble signal (descramble signal) and is supplied to the input on one side of the exclusive-OR gate 32g. The input on the other side of the exclusive-OR gate 32g receives the data to be scrambled (or descrambled). The exclusive-OR gate 32g outputs scrambled (or descrambled) data.
The above-described scrambling/descrambling circuit performs scrambling/descrambling using the following generating polynomial: EQU g(x)=x.sup.5 +x.sup.2 +1
The scrambling circuit 32 (or descrambling circuit 35) may be alternatively constructed as shown in FIG. 10. In FIG. 10, the scrambling circuit 32 comprises a counter 41, a ROM 42, and exclusive-OR gates 43a through 43h. This circuit, too, scrambles (or descrambles) signals using the same generating polynomial as that for the circuit of FIG. 9. In this case, the clock cycle is 31(2.sup.5 -1) since the generating polynomial above has degree five. The counter 41, which counts input clock pulses, supplies the ROM 42 with a count value between 0 and 31 as an address. In this example, eight exclusive-OR gates 43a through 43h process input data in parallel, eight bits at a time. Thus the ROM 42 contains beforehand 248 bits of data, the bit count being the least common multiple of 31 and 8. Every time an address is designated, eight bits of data are supplied to the inputs on one side of the exclusive-OR gates 43a through 43h. The inputs on the other side of the exclusive-OR gates 43a through 43h receive eight bits of parallel data to be scrambled (or descrambled). In this manner, the exclusive-OR gates 43a through 43h output the scrambled (or descrambled) data.
The typical scrambling (descrambling) circuit of FIG. 9 is required to operate at a bit clock rate commensurate with the transmission rate at which scrambled (or descrambled) data are output one bit at a time. One disadvantage of this arrangement is that in the TTL or CMOS process, the circuit operates at rates of tens of MBPS at most. That is, it is difficult for circuits of this type to transmit high-definition television (HDTV) data and the like to be transmitted at rates of 100 MBPS or higher. One ramification of this aspect is that the scrambling (descrambling) circuit can not be put into LSI format if manufactured as a CMOS arrangement; the circuit must be constructed as an ECL setup.
The scrambling (descrambling) circuit of FIG. 10 processes eight bits of data at a time. This means that the counter 41 need only operate at one-eighth of the bit transmission rate. However, if this circuit is to be constructed in discrete format, the need to incorporate the counter 41, ROM 42 and exclusive-OR gates 43a through 43h means not only higher cost but also more space to accommodate them. In LSI format, the circuit is required to allocate a disproportionately large space to the ROM 42. These disadvantages are increasingly pronounced as the degree of the generating polynomial is raised. Thus, under the prior art constraints it is difficult to adopt a generating polynomial of a substantially high degree in connection with the manufacture of the scrambling/descrambling circuit.